Not applicable.
This invention is in the field of semiconductor assembly, testing, and packaging.
An integrated circuit in its unpackaged state is susceptible to damage and its small size and dense features cause difficulties when interconnecting the integrated circuit with other electronic components in a system. Consequently, an integrated circuit is typically packaged in plastic or ceramic and the interconnection problems are solved by leads extending from the plastic or ceramic package material, or in the case of a Ball Grid Array (BGA) package, by solder balls attached to contact pads on the bottom side of the device package. FIG. 1 is a side cross-sectional view of a leaded, packaged integrated circuit, hereinafter referred to as a xe2x80x9csemiconductor devicexe2x80x9d. The integrated circuit 10 is mounted on a leadframe 12. Electrical connection between the integrated circuit 10 and the leads 14 is established by bond wires 16. The integrated circuit 10, the leadframe 12, the bond wires 16, and a portion of leads 14 are encapsulated in packaging material 18, which is typically plastic or ceramic. Leads 14 are bent into a gullwing shape that is suitable for surface mounting. Well-known package types such as the Thin Small Outline Package (TSOP) and the Quad Flat Package (QFP) typically have the features shown in FIG. 1. FIG. 2a is a top view of a square QFP semiconductor device showing plastic encapsulant 20 with leads 22 along all four sides of the device. FIG. 2b is a side view of the QFP semiconductor device illustrating the shape of the leads.
In practice, the semiconductor device is mounted on a printed circuit board (PCB) with electrical connection between the leads and the pads on the PCB established with solder. Coplanarity of the leads is important in order to ensure that all leads properly contact the appropriate pads on the PCB. However, leads are easily bent, in particular in testing and burning-in of the device, in packing and shipping of the device, as well as in the assembly process in which the device is mounted on a PCB. Consequently, a need has been recognized by the electronics industry to establish standards for lead coplanarity. An example is JEDEC Standard JESD22-B108 xe2x80x9cCoplanarity Test for Surface-Mount Semiconductor Devices.xe2x80x9d Equipment manufacturers have responded by developing optical/laser systems for measuring deviations of leads from coplanarity. Coplanarity inspection typically consists of laser triangulation to map the coordinates of the leads of the package, or in the case of BGA, the solder balls, relative to the other leads or balls. Once the coordinates have been measured, a seating plane including the lowest three leads or solder balls is calculated. Automated software then determines whether the remaining leads or balls are within a specified distance above the seating plane. Unfortunately, these prior art techniques suffer from shortcomings that can result in an unacceptable failure rate when the semiconductor device is mounted on a PCB. This is particularly true when the seating plane is determined by three leads or balls in close proximity to one another, or when the package is warped.
The JEDEC test JESD22-B108 consists of measuring the distance between the intended contact point of a lead and a seating plane. The seating plane is defined as the plane established by the contact points of three or more leads that support the device when it is placed on top of a planar surface. FIGS. 3a and 3b show an example of a seating plane 32 calculated using the JEDEC test. The lowest three leads 34 are the corners of the triangle and the maximum lead distance above the seating plane is the lead coplanarity 36 for the particular device shown. The center of gravity 30 of the device is indicated in FIG. 3a. Equipment vendors have developed systems that establish the seating plane and measure the deviation of the leads from coplanarity as required by the standard. However, in an unacceptable number of cases, devices that pass this test later fail coplanarity tests when mounted on a PCB. The JEDEC test assumes the device is mounted on a planar surface. A PCB is often far from ideally planar. In addition, some measurement equipment measures coplanarity deviation from the top side of the lead, a technique which assumes that all leads are of the same thickness. A variation in thickness of the leads can change the seating plane measured in the JEDEC test. Some equipment measures coplanarity while the devices are packed in trays, creating potential for miscomputation of the seating planes. For larger packages in particular, there is potential for tilting and a change of seating plane, not only from lead thickness variations, but also from downward force applied during component placement and during wave-soldering when solder paste under the leads typically loses significant volume, for example. Variations in solder paste applied to the PCB solder pads on which the leads sit could also be a problem. Of course, any device warpage or variations in the lead forming angle will exacerbate the deviations from lead coplanarity. Similar problems apply to BGA packages.
In response to the shortcomings of the single seating plane method described above, the test and measurement industry has developed a dual seating plane method for predicting coplanarity problems. The single seating plane method is particularly inadequate in situations where the center of gravity of the device is contained within a narrow seating plane triangle, or when a side of a narrow seating plane triangle passes through the center of gravity. Such a situation is shown in FIGS. 4a and 4b. In FIG. 4a, the seating plane 42 has an edge passing through the center of gravity 40. In addition, the seating plane triangle 42 is relatively narrow, which results in a tendency of the device to tilt. The prior art dual seating plane method therefore assumes that the device will tilt and calculates a new seating plane 44 based on the predicted tilt. The lead coplanarity 46 is determined relative to this tilted plane 44. One disadvantage of this approach is that it depends upon a determination of whether the seating plane is narrow or not. If a narrow plane is mistakenly detected as non-narrow, significant errors in determining lead coplanarity will result. Furthermore, in selecting the new seating plane 44, the prior art dual seating plane method does not systematically choose the corner pins as one or more of its seating points. Rather, it selects a lead based on a pre-determined formula, such as the lowest lead twenty leads away from the previous lead on either side of the center of gravity of the device, and then calculates the worst-case coplanarity deviation for the original as well as these additional seating planes. This creates a situation in which the device could again tilt from the selected seating plane; if, for instance, the new planes are narrow or if the new seating planes are not near the corners. In summary, this dual plane method is an improvement over the single plane method, but still is inadequate in predicting worst case coplanarity, particularly in situations where warpage of the semiconductor device is present. The inadequacies of the prior art methods lead to screening errors that can result in either a lower device yield than is necessary, or in a customer receiving out-of-specification devices, neither of which is acceptable.
In an embodiment of the invention, a method for determining contact coplanarity of packaged semiconductor devices having a plurality of contacts is disclosed. The method includes the steps of measuring the relative positions of the contacts on a subject semiconductor device; calculating from the measurements seating planes formed by tilting the device to one or more of its corners and/or sides such that each said plane comprises contacts at or adjacent to the corners of the device; using the measured relative contact positions and the calculated seating planes to determine the highest deviation from contact coplanarity for the semiconductor device.
In another embodiment of the invention, a method for screening for contact coplanarity packaged semiconductor devices having a plurality of contacts is disclosed. The method includes the steps of measuring the relative positions of the contacts on a subject semiconductor device; calculating from the measurements seating planes formed by tilting the device to one or more of its corners and/or sides such that each said plane comprises contacts at or adjacent to the corners of the device; using the measured relative contact positions and the calculated seating planes to determine the highest deviation from contact coplanarity for the semiconductor device; and comparing the highest deviation from contact coplanarity to a pre-determined specification.
In still another embodiment of the invention, a semiconductor test apparatus is disclosed. The apparatus includes a tool operable to measure the relative positions of contacts on a packaged semiconductor device and a computer operable to use the relative positions to determine seating planes formed by tilting the device to one or more of its corners and/or sides such that each said plane comprises contacts at or adjacent to the corners of the device. The computer is further operable to calculate a highest deviation from contact coplanarity using the measured relative contact positions and the seating planes.
An advantage of the invention is that it enables efficient screening of semiconductor devices for worst-case deviations from lead coplanarity. The inventive methods and apparatus were developed in view of the fact that semiconductor devices are typically placed on a PCB having a rough and uneven surface.